1. Field of the Invention
The present invention relates to a circuit substrate and a method of manufacturing the same. The present invention also relates to a semiconductor device, a method of manufacturing the same, and a system that employs them. The present invention also relates to a wafer-level packaging structure and a method of manufacturing the same.
2. Description of the Related Art
In recent years, there has been an explosion of demand for miniaturization of circuit systems utilizing semiconductor chips, such as computers, mobile communication devices, and the like. To meet such demand, semiconductor chips may be mounted in the form of chip-size packages (CSP) that are close in size to the chips.
One well-known method of implementing CSPs is a packaging method called “wafer-level packaging” (WLP) (see Japanese Patent Laid-open Publication No. 2004-319792 and Japanese Patent Laid-open Publication No. 2007-157879). WLP is a method, in which an external terminal electrode and the like are formed on a silicon wafer prior to its singulation by dicing, with singulation by dicing performed after WLP. It is expected that the use of WLP may be able to increase productivity because an external terminal electrode and the like can be formed simultaneously on multiple semiconductor chips.
However, high production costs present a problem for WLP because it is a step carried out subsequent to the front-end-of-line steps used to manufacture a substrate with internal terminal electrode, and because, unlike regular packaging methods utilizing bonding wires, it normally includes photolithography steps (resist coating, exposure, development, and resist stripping) among the back-end-of-line processing steps used to finish the final product containing the substrate. For example, a method, in which external terminal electrode (31) is formed after patterning a wiring layer (12) using a photolithographic process and then patterning an insulating layer (21) using a photolithographic process, is depicted in FIG. 9 of Japanese Patent Laid-open Publication No. 2004-319792. In addition, a method, in which external terminal electrode (16) is formed after patterning a wiring layer (13) using a photolithographic process and then patterning an insulating layer (15) using a photolithographic process, is also depicted in FIGS. 3-4 of Japanese Patent Laid-open Publication No. 2007-157879.
Such problems are not limited to semiconductor chip WLP and also occur in other cases, in which external terminal electrode is formed on various circuit substrates having fine internal circuitry formed therein.
Accordingly, there is a need for a less expensive method of forming external terminal electrode on circuit substrates having fine internal circuitry formed therein, especially on silicon wafers at wafer level.
Furthermore, the present inventors have also noted the following. For example, when contemplating a system-in-package (SIP) semiconductor device having a mixture of circuit substrates and other function chips mounted thereon, mounting in a package (CSP) that is close in size to the semiconductor chips contained in the package is preferable in terms of the package size of the semiconductor device. For instance, when a first chip contained on a circuit substrate and a second chip that communicates with the first chip are of different chip sizes, chip-level mounting technology is required to combine these chips into a laminate structure. Packaging multiple chips as a single unit at wafer level is preferable for further miniaturization and price reduction.
In addition, when, for example, multiple second chips are laminated on a wafer comprised of multiple corresponding first chips and the chips are connected using bonding wires, redistribution wiring (redistribution wiring layers) connected to the bonding wires has to be formed on the wafer. However, in terms of its metal, Cu wiring produced by additive (damascene) plating subsequent to sputtering regular underlying metallization is not particularly suitable for connection to bonding wires due to wettability and other problems. As a result, gold plating has to be additionally applied to the Cu wiring layer used as the redistribution wiring, thereby producing a redistribution wiring layer structure that is multi-layered and fraught with high production costs.